Search results for "Gate dielectric"
showing 10 items of 12 documents
Effects of water dielectric saturation on the space–charge junction of a fixed-charge bipolar membrane
2000
Abstract The dielectric saturation at the space–charge junction of a fixed-charge bipolar membrane is studied using the theoretical approach by Booth for the water dielectric constant and the Poisson equation for the electrical double layer at the junction. The numerical solution gives the electric field and dielectric constant profiles through the junction as well as the junction thickness as a function of the voltage drop. The water dielectric constant decreases substantially for the large electric fields that may occur at the narrow bipolar junction.
Location of holes in silicon-rich oxide as memory states
2002
The induced changes of the flatband voltage by the location of holes in a silicon-rich oxide (SRO) film sandwiched between two thin SiO 2 layers [used as gate dielectric in a metal-oxide-semiconductor (MOS) capacitor] can be used as the two states of a memory cell. The principle of operation is based on holes permanently trapped in the SRO layer and reversibly moved up and down, close to the metal and the semiconductor, in order to obtain the two logic states of the memory. The concept has been verified by suitable experiments on MOS structures. The device exhibits an excellent endurance behavior and, due to the low mobility of the holes at low field in the SRO layer, a much longer refresh …
Electric breakdown of dielectric thin films for high-voltage display applications
2016
Smectic A liquid crystal is one of the most promising material for smart glass application due to infinite bistability and low haze at clear state. Voltage is needed to switch from scattering to transparent and it is likely for dielectric breakdown to occur. In order to reduce the probability of dielectric breakdown to occur, a dielectric insulating coating is usually employed. In this work we have compared electrical and optical properties of SiO2 thin films with thickness up to 500 nm coated by flexographic printing and reactive magnetron sputtering. IV characteristics and dielectric breakdown values show sputtered coatings to have higher dielectric strength. For sputtered coatings with t…
Nanostructural depth-profile and field-effect properties of poly(alkoxyphenylene-thienylene) Langmuir-Schäfer thin-films
2008
The correlations between morphological features and field-effect properties of poly(alkoxyphenylene-thiophene) thin Langmuir–Schafer film deposited on differently terminated gate dielectric surfaces, namely bare and methyl functionalized thermal silicon dioxide (t-SiO2), have been systematically studied. The film morphology has been investigated at different film thickness by Scanning Force Microscopy. Films thicker than a few layers show comparable morphology on both dielectric surfaces while differences are seen for the ultra-thin polymer deposit in close proximity to the substrate. Such deposit is notably more heterogeneous on bare t-SiO2, while a more compact and uniform nanogranular st…
Effect of high-k materials in the control dielectric stack of nanocrystal memories
2004
In this paper we studied program/erase characteristics by FN tunneling in Si nanocrystal memories. Starting from a very good agreement between experimental data and simulations in the case of a memory cell with a thin tunnel oxide, Silicon dots as medium for charge storage, and a CVD silicon dioxide used as control dielectric, we present estimated values of the charge trapping when a high-k material is present in the control dielectric. We then show preliminary results of nanocrystal memories with control dielectric containing high-k materials. ©2004 IEEE.
High-Speed Memory from Carbon Nanotube Field-Effect Transistors with High-κ Gate Dielectric
2009
We demonstrate 100 ns write/erase speed of single-walled carbon nanotube field-effect transistor (SWCNT-FET) memory elements. With this high operation speed, SWCNT-FET memory elements can compete with state of the art commercial Flash memories in this figure of merit. The endurance of the memory elements is shown to exceed 104 cycles. The SWCNT-FETs have atomic layer deposited hafnium oxide as a gate dielectric, and the devices are passivated by another hafnium oxide layer in order to reduce surface chemistry effects. We discuss a model where the hafnium oxide has defect states situated above, but close in energy to, the band gap of the SWCNT. The fast and efficient charging and discharging…
Effect of humidity on the hysteresis of single walled carbon nanotube field-effect transistors
2008
Single walled carbon nanotube field-effedt transistores (SWCNT FETs) are attributed as possible building blocks for future molecular electronics. But often these transistors seem to randomly display hysteresis in their transfer characteristics. One reason for this is suggested to be water molecules adsorbed to the surface of the gate dielectric in this study we investigate the thysteresis of SWCNT FETs at different relative humidities. We find that SWCNT FETs having atomic layer deposited (ALD) Hf0 2 -Ti0 2 .- Hf0 2 as a gate dielectric retain their. ambient condition hysteresis better in dry N2 environment than the more commonly used SiO 2 gate oxide.
High-Yield of Memory Elements from Carbon Nanotube Field-Effect Transistors with Atomic Layer Deposited Gate Dielectric
2008
Carbon nanotube field-effect transistors (CNT FETs) have been proposed as possible building blocks for future nano-electronics. But a challenge with CNT FETs is that they appear to randomly display varying amounts of hysteresis in their transfer characteristics. The hysteresis is often attributed to charge trapping in the dielectric layer between the nanotube and the gate. This study includes 94 CNT FET samples, providing an unprecedented basis for statistics on the hysteresis seen in five different CNT-gate configurations. We find that the memory effect can be controlled by carefully designing the gate dielectric in nm-thin layers. By using atomic layer depositions (ALD) of HfO$_{2}$ and T…
Ultra-Low Noise Multiwalled Carbon Nanotube Transistors
2013
We report an experimental noise study of intermediate sized quasi ballistic semiconducting multiwalled carbon nanotube (IS-MWCNT) devices. The noise is two orders of magnitude lower than in singlewalled nanotubes (SWCNTs) and has no length dependence within the studied range. In these channel limited devices with small or negligible Schottky barriers the noise is shown to originate from the intrinsic potential fluctuations of charge traps in the gate dielectric. The gate dependence of normalized noise can be explained better using ballistic the charge noise model rather than diffusive McWhorter’s model. The results indicate that the noise properties of IS-MWCNTs are closer to SWCNTs than th…
Semi-Empirical Model for SEGR Prediction
2013
The underlying physical mechanisms in single event gate rupture (SEGR) are not known precisely. SEGR is expected to occur when the energy deposition due to a heavy ion strike exceeds a certain threshold simultaneously with sufficient electric field across the gate dielectric. Typically the energy deposition is described by using the linear energy transfer (LET) of the given ion. Previously the LET has been demonstrated not to describe the SEGR sufficiently. The work presented here introduces a semi-empirical model for the SEGR prediction based on statistical variations in the energy deposition which are described theoretically.